1. Field of the Invention
The present invention relates to a high-speed MOS-technology power device integrated structure, e.g. a power MOSFET or an Insulated Gate Bipolar Transistor (IGBT), and to a related manufacturing process.
2. Discussion of the Related Art
The need is known for high-speed (i.e. low switching time) MOS-technology power devices, for example in the field of Zero Crossing Switch (ZCS) power supplies wherein frequencies of up to 2 MHZ are common.
A MOS-technology power device chip includes a matrix of many millions of elementary vertical MOSFET units which individually contribute to the overall current of the power device; typically, the elementary units are polygonal-plan cells including a body region of the P conductivity type formed in a lightly doped semiconductor layer of the N conductivity type; the body region including a channel region which is covered by an insulated gate layer, i.e. a thin oxide layer and a polysilicon layer, forming a mesh over the surface of the N type layer; an N type annular source region is formed inside the body region. An insulating material layer covers the surface of the chip.
Narrow gate metal (aluminum) fingers connected to a gate metal pad extend on the surface of the chip to contact the underlying polysilicon gate layer through contact windows in the insulating material layer, and are interdigited with wider source metal fingers which, also through windows in the insulating material layer, contact the source regions and the body regions of all the elementary cells. The gate metal fingers are spaced about 1 mm, corresponding to about 60 elementary cells.
Due to the relatively high resistivity of polysilicon (50 Ohm/square) with respect to aluminum (10-3 Ohm/square), a gate resistance is introduced between the gate metal pad and cells. Such a resistance, together with the input capacitance of the elementary cells, forms an RC circuit, and is one of the main parameters affecting the speed of the power device.
A straightforward solution to this problem consists in augmenting the number of the gate metal fingers, thus reducing the spacing between them: if necessary, one gate metal finger every one elementary cell can be provided; in this way, the gate resistance of the elementary cells is obviously reduced, but a lot of chip area is wasted; while in fact the source metal fingers extend over the elementary cells, no elementary cells can be integrated under the gate metal fingers. Furthermore, the width of the source metal fingers must be reduced and their number must be correspondingly increased, with the consequence of a reduced uniformity in the source current distribution.
In view of the state of the art just described, it is an object of the present invention to provide a MOS-technology power device integrated structure wherein the gate series resistance can be reduced without necessarily augmenting the number of the gate metal fingers.